00889nam a2200181Ia 4500008004100000100002600041245005400067250000600121260001200127260000900139300000800148650004000156942001000196952015400206952016600360952016600526999001500692221231s9999    xx            000 0 und d  aPalnitkar,Samir95298 0aVerilog HDL guide to digital design and Synthesis  a2  bPearson  c2008  a490  aElectronics and Communication95299  cBE_BK  00104070aAITbAITd2015-06-24eBook Paradiseg350.00l0pBE10969r2022-12-31v350.00w2022-12-31yBE_BKzElectronics and CommunicationB1900-01-01  00104070aAITbAITd2015-06-24eBook Paradiseg350.00l2pBE10970r2024-12-18s2024-09-30v350.00w2022-12-31yBE_BKzElectronics and CommunicationB1900-01-01  00104070aAITbAITd2015-06-24eBook Paradiseg350.00l1pBE10971r2023-03-09s2023-02-09v350.00w2022-12-31yBE_BKzElectronics and CommunicationB1900-01-01  c3955d3955